1. Field of the Invention
This invention relates to semiconductor devices, and more particularly to planarized contacting of semiconductor devices such as high power heterojunction bipolar transistors (HBTs).
2. Description of the Related Art
HBTs are described in general in Wang, Introduction to Semiconductor Technology: GaAs and Related Compounds John Wiley & Sons, 1990, pp. 170-230. Some of the advantages of HBTs over other transistors such as FETs include; short transition times because of their vertical structure, higher current handling capability per unit chip area, which contributes to higher output drive capabilities, and increased transconductance.
There is a continuing need to develop integrated circuits and components, including HBTs, which operate at higher frequency or speeds, with reduced power. This design goal places a greater emphasis on increased component integration and packing density, which results in decreased feature sizes, increased interconnection complexity and use of new or specialized materials.
One of the concerns in fabricating semiconductor devices such as HBTs is reliably making electrical contact to the different epitaxial layers (emitter, base and collector layer for HBTS), and isolating devices electrically by eliminating or rendering inactive the epitaxial layers outside of the transistors. In fabricating conventional HBTs, epitaxial layers are grown vertically to form the HBT's active layers. To contact the HBT's emitter layer a contact metal can be deposited on the device's top surface, which is generally an emitter contact layer. To contact the base layer, the emitter contact layer and emitter layer are etched (except under the emitter contact) to provide a surface on the base layer for depositing a contact metal. To contact the collector layer, portions of the emitter contact layer, emitter layer, base layer and collector layers are etched to provide a surface on a sub-collector layer for depositing the contact metal.
Before electrical connection to the contact metals, conventional HBTs are covered with a passivation material. The emitter, base and collector metals are then contacted through the passivation material, by etching a via pathway through the passivation material down to each contact metal. A conductive material is then deposited in the etched areas to form conductive vias to the contact metals. Electrical connection is made to the HBT's active layers by connection to the conductive vias.
One disadvantage of this technique is that it cannot be used to reliably contact high speed HBTs. To increase the speed of HBTs, the emitter becomes smaller and the size of the emitter correlates to the size of its contact metal. As the emitter is reduced, a point is reached where the emitter metal cannot be reliably contacted by using conductive vias. The resolution and alignment limits of lithography and etch systems limit how small the device features can be for HBTs. The smallest resolution for etching a via through polymide or BCB over an emitter metal is approximately 0.5 μm. The emitter should be 0.2 μm wider than the width of the via to provide a margin of error in case the via is not perfectly aligned over the emitter metal. Accordingly, the smallest the emitter can be is approximately 0.75 μm wide.
Another concern is that for smaller emitters the via etch may not align with the emitter metal. This can result in the etch extending beyond the emitter metal to the epitaxial layer. When the via etch is filled with the conductive material to form the via, the conductive material can form a short to the epitaxial material that bypasses the emitter metal, emitter contact layer and emitter layer. This naturally results in a greater number of fabrication errors, making the HBTs less reproducible.
Planarization has been used to remedy surface topologies that can create problems for a semiconductor device's performance and survivability [See U.S. Pat. No. 4,996,165 to Chang et al.]. Variations in feature height, topography or morphology can lead to stress in subsequently deposited layers or materials and height variations in one layer can make precise control of the dimensions of subsequent layers difficult. The features of a semiconductor device are formed by depositing a layer of photoresist on an upper layer of the structure and developing it in a desired pattern. After development and etching, some photoresist remains on the upper surfaces of the features. A layer of dielectric material such as SiO is deposited across the semiconductor structure to a depth substantially the same as the height of the tallest features. The remaining photoresist is then removed along with the dielectric deposited thereon. A layer of polymide is deposited on the upper surface of the SiO and features, and extends into depressions between to control the height variations.